Joe Fioti, in a post on X published July 15, argued that one hardware pattern now carries most of the arithmetic inside AI chips: the systolic array. He says it handles over 95 percent of compute in modern accelerators. Chipmakers spend billions competing on transistor counts and clock speeds. Fioti’s framing puts the real differentiator elsewhere: how efficiently data moves once it is already on the chip. Values pass between neighboring processing elements instead of shuttling back to memory, and that local routing is what cuts the traffic that otherwise limits throughput.

The pattern is not new. Google described a similar array in its first Tensor Processing Unit, detailed in a 2017 paper on the chip’s design. Values loaded once get reused across many multiply-accumulate steps as they pass from one processing element to the next, which is the mechanism Fioti is describing. Nvidia’s tensor cores, introduced with the Volta architecture, apply a related approach inside a general-purpose GPU.

The underlying economics explain why array size matters at all. Memory bandwidth on accelerator chips has grown through successive generations of high-bandwidth memory, but each generation of compute logic has added arithmetic capacity faster than it has added bandwidth to feed it. That gap, sometimes called the memory wall, is why chip designers keep adding on-chip cache and local buffers instead of simply enlarging the array without limit.

Fioti’s second point, that larger arrays are harder to keep full, describes that same constraint from the compiler’s side. As an array’s compute capacity grows faster than the bandwidth feeding it, the array runs out of data before it runs out of math to do. Closing that gap falls to software: how the matrix multiplication gets tiled and scheduled decides whether a chip converts its rated peak into delivered throughput. Compiler stacks built for exactly this problem, among them Google’s XLA and the open source TVM project, exist to handle that tiling and scheduling work.

Fioti’s post does not name a chip that misses its rated peak, nor does it cite a benchmark showing the size of the gap. The observation reads as a structural argument about hardware economics, not a report on one product’s performance.

A peak-FLOPS number on a spec sheet answers little on its own. Ask any vendor for measured utilization on your actual matrix shapes. Ask what their compiler stack does to keep the array fed before signing a multi-year hardware contract.

Joe Fioti, in a post on X on July 15, 2026.