Nvidia has reportedly tested at least three reduced-memory builds of its unreleased Rubin Ultra accelerator, with capacities running as low as 192GB, according to a report from The Information that Tom’s Hardware relayed on August 10, 2026. The report also affirms an earlier note from the analysis firm SemiAnalysis, which had flagged a possible Rubin Ultra memory cut before Nvidia’s testing was confirmed.
The stakes are set by what Nvidia showed at GTC earlier this year: a compute tray carrying four chiplets and 1 TB of HBM4E, positioned as the core of the Kyber NVL144 rack scheduled for a 2027 rollout. A cut of that scale, even if only tested rather than finalized, would reset expectations for the chip’s headline spec.
Nvidia has pushed back on a related claim. After SemiAnalysis reported the surrounding Kyber rack had slipped to 2028, Nvidia told Tom’s Hardware its “roadmap is intact,” without clarifying whether the delay itself was accurate.
Beyond the 192GB figure, Nvidia is reportedly also testing a 256GB tier and versions using fewer than the 16 memory stacks originally announced. The more consequential detail may be the memory type: some prototypes reportedly drop back to HBM4 rather than the newer HBM4E Nvidia had planned to use.
HBM4E’s key feature, a base logic die that customers can customize, was made possible by a partnership Micron struck with TSMC last year to manufacture that die. That extra complexity appears to be exactly what has slowed supply: memory suppliers reportedly cannot produce HBM4E fast enough to match Rubin Ultra’s launch schedule.
Die count adds another wrinkle. June reporting held that Nvidia dropped a four-die Rubin Ultra layout over manufacturing issues in favor of a two-die design, a shift that would make a smaller memory footprint easier to justify. Even so, the lowest figures under test undercut what a two-die chip alone would suggest: the standard Rubin GPU shipping today already carries 288GB of HBM4 by itself.
Memory, not compute, has become the binding constraint on inference economics for frontier-scale models. VRAM decides how many parameters and how much context fit on a single accelerator before a workload must be split across multiple chips, which adds latency and cost. A flagship design stepping down in memory, even as a tested option rather than a locked-in spec, is fundamentally a supply story, and it carries a direct consequence for deployment: fewer gigabytes per chip means more chips per model for the same workload.
Nvidia has spent the year locking down memory access years ahead of shipment. In June, the company struck a multi-year co-development and supply agreement with SK hynix covering HBM, LPDDR5X, and DDR5. It widened that arrangement in July into a $500 billion agreement with a long-term HBM supply component. The Information also quoted a customer of Nvidia’s saying gigabytes per chip isn’t what drives their purchasing decision. What matters more, this customer said, is the long-run relationship with Nvidia.
The squeeze reaches well past Rubin Ultra. Digitimes reported last week that HBM capacity at SK hynix, Samsung, and Micron is already booked through 2027, leaving no near-term spot supply. SK hynix chief executive Kwak Noh-jung said last month that 2027 will mark the low point of the shortage, with tight supply persisting through 2030, a window that outlasts Rubin Ultra’s entire planned production run.
Buyers planning 2027 deployments on Rubin Ultra should treat the 1TB spec as provisional, not guaranteed, and revisit how many accelerators their target models actually require before locking in capacity commitments.
This article is based on reporting by Tom’s Hardware, published August 10, 2026, which cited The Information and SemiAnalysis.
