Google Reportedly Taps AMD to Design a CPU-Heavy TPU

Google is reportedly working with AMD on a new variant of its TPU accelerator line that would place general-purpose CPU cores on the same package as the tensor silicon, according to a SemiAnalysis client note relayed by an X account called Sean and reported by Tom’s Hardware. The design in question would belong to Google’s upcoming tenth-generation TPU family and appears aimed less at general model training than at reinforcement learning and other workloads that lean heavily on ordinary compute.

The distinction matters because reinforcement learning does not behave like pretraining. Pretraining is close to pure matrix multiplication, which is exactly what a TPU is built to chew through. RL adds a second, parallel job: running the simulators or environments an agent operates in, scoring the outputs, computing a reward signal, and feeding that back into the next training step. Those tasks run on ordinary processors, not tensor cores, and they happen constantly, interleaved with the accelerator math rather than running once at the start.

That interleaving is where the current setup loses time. When the CPU work and the tensor work live on separate packages, every handoff between them costs latency and power. SemiAnalysis’s note, as relayed by Tom’s Hardware, says Google, together with its customers, wants TPUs carrying CPU cores inside the package specifically to shrink that gap, rather than routing RL’s general-purpose workload through a distant host processor.

Google’s own hardware trend supports the logic. Its TPU 8i systems, built for inference, reasoning, and RL, ship with one Google Axion CPU paired against every two TPUs, a much richer ratio than the one Xeon Emerald Rapids chip Google used for every four TPUs on its seventh-generation deployments. Tom’s Hardware reports hearing that some workloads now call for CPU and accelerator counts that are close to even, which suggests the compute mix behind reasoning and agentic AI is shifting toward general-purpose silicon faster than most infrastructure roadmaps assume.

AMD’s role, as described, is narrower than “AMD designs the next TPU.” Google has shipped nine TPU generations with Broadcom doing the physical chip design, and Tom’s Hardware notes Google has little need for outside help on a conventional accelerator. What AMD reportedly brings instead is CPU intellectual property, advanced packaging expertise, and a working precedent: the Instinct MI300A, a chip AMD already ships that fuses x86 cores and accelerator silicon into one package. That precedent is reportedly the reason AMD, rather than Intel or Broadcom, is in the conversation for the CPU portion of this design.

The AMD detail is the part worth sitting with. Google’s TPU program is the standard proof point that a hyperscaler can build its way out of dependence on Nvidia’s GPUs, and bringing in a second silicon partner for even one component signals that Broadcom is not the only company Google trusts with chip design at this scale. AI Insiders covered two connected threads this week: an argument that Nvidia’s core product is less the chip than the financing arrangement that keeps customers tied to it, and Nvidia’s own decision to walk back a data-center guarantee it had extended to OpenAI. A custom TPU built with whichever partner holds the right expertise, instead of the incumbent one, is what that kind of exit from Nvidia’s orbit looks like at the design-partner level, not just the balance-sheet level.

None of this is confirmed. The report traces back to a SemiAnalysis note for paying clients and a secondhand post on X, and Tom’s Hardware is explicit that its own analysis could be wrong. Google has not acknowledged a tenth-generation TPU split by workload, an AMD partnership, or any on-package CPU design.

Teams building RL or agentic training pipelines on Google Cloud should treat a CPU-rich TPU as a roadmap signal to watch, not infrastructure to plan around yet. If it materializes, the number worth tracking will be the CPU-to-accelerator ratio on the spec sheet, not peak FLOPS.

Tom’s Hardware reported on August 16, 2026, citing a SemiAnalysis client note relayed by an X account called Sean.