Extropic, a startup building computer chips that compute with electrical noise instead of clean binary logic, has published results for Z1T, a new family of sparse transformer-like models built to run on its Z1 chip. The company projects the pairing could cut the energy cost of running a transformer by roughly two orders of magnitude compared with an Nvidia H100, and says removing a current bottleneck could push that toward three orders of magnitude. Extropic has not shipped a working system that runs Z1T end to end at those figures.
The wager is a different kind of chip. Ordinary processors spend a large share of their power budget forcing millions of transistors to behave as clean, deterministic switches, fully on or fully off, with margins built in to keep noise out. Extropic’s Z1 chip does the opposite. It runs its circuits, called pbits, in a regime where their output is genuinely random, then treats that randomness as the computation itself rather than as a flaw to correct. Each pbit samples a value based on its neighbors, the way a unit in a Boltzmann machine draws a sample, and the chip wires 16 such couplings around every pbit. Removing the deterministic guardrails is what makes the chip cheap to run. It also means a model has to be redesigned around sampling instead of ordinary arithmetic.
That redesign is Z1T. Because Z1’s pbits are wired with fixed, sparse connectivity baked into the silicon, a model has to be built around sparse operations from the start rather than pruned down after training dense. Extropic trained a range of Z1T sizes to trace a scaling law and found the sparse models need roughly ten times the training compute of a standard GPT-2-style model to match its loss. Extropic’s argument is that the per-operation energy on Z1 sits low enough that the larger FLOP count still nets out to a big efficiency gain.
Extropic is precise about what has and has not actually been measured, and the distinction matters. The Z1 chip itself is fabricated silicon: eight cores, 269,568 pbits, sampling at 50 megahertz, drawing under a watt. But Z1’s first generation ships paired with an FPGA co-processor that handles everything the chip cannot do natively, and the reported per-token energy and latency numbers describe that hybrid pipeline, not the chip alone. Extropic says the FPGA accounts for more than 95 percent of the pipeline’s energy use.
The headline efficiency figures are explicitly labeled projections. Extropic calculated them from a theoretical model of Z1’s power draw, anchored to measurements taken on an earlier, related chip called X0, not from a Z1T system running end to end. Only the H100 comparison point was directly measured, on August 12. Extropic is also open sourcing its Z1T training recipes and the weights for one of its larger training runs, a genuine and checkable release even if the energy math is not yet.
Novel computing substrates have a long history of dazzling in simulation and disappointing once fabricated at scale: memristors, optical processors, and earlier analog accelerators all produced striking projected numbers that shrank once real parts shipped in volume. The figure worth tracking here is not the 100x, or eventual 1000x, Extropic is advertising. It is whether Z1T ever runs on hardware an outside lab can put a power meter on.
Teams evaluating inference hardware for 2027 budgets should file Z1T as a research direction, not a procurement input, until an independently measured chip ships.
Extropic published the Z1T results and methodology in its own technical post, “Z1T: Sparse Transformer-Like Models for Probabilistic Hardware,” on its company site.
